The invention relates to a storage arrangement with modules consisting of CCD stores.
CCD stores are known, for example, from the article "Charge Coupled Semiconductor Devices" in "The Bell System Technical Journal," 49, April 1970, pages 587-593. In Multi-phase CCD modules, the storage of one information bit requires at least two storage electrodes, and at any one time, the information bit is located beneath one of these electrodes. When shifted onwards, the information bit is moved under a second storage electrode which is not in use.
The storage positions are arranged in a series in the form of shift registers on the modules, and the individual shift registers are connected to one another in different ways. Here, first, two fundamental circuits are conceivable: In the one, the data transfer always occurs in one direction, e.g., from left to right, but this necessitates long line lengths in the event of the chaining of the shift registers either parallel to the channels with the storage positions or around the storage field. The other fundamental circuit means a zig-zag operation in which those ends of the shift registers which are adjacent one another are directly connected to each other, so that the data transfer takes place, e.g., from left to right in one shift register and from right to left in the underlying shift register. However, this necessitates a crossing over of the pulse train lines between adjacent shift registers, i.e., the actual storage surface is smaller with a constant module size.
These topographic disadvantages associated with the routing problems of pulse train drive devices have led to a different structure, the so-called series-parallel-series (SPS) arrangement which permits a higher store density. This arrangement is described, for example, in "The Journal of Vacuum Science and Technology," Vol. 9, No. 4, 1972, pages 1166-1180, in particular in Chapter XII, and is illustrated in FIG. 22.
In this known arrangement a CCD module in each case contains an input and an output shift register each with three electrodes per bit, and, correspondingly, three pulse trains. These pulse trains determine the data rate of the module. The items of data are transported in serial fashion in the shift registers. The actual storage area contains as many parallel shift registers as the input and output shift registers possess storage positions. From the serial input register, the items of data are transferred in parallel into the storage area and thus are displaced in parallel to the output shift register. This avoids cross-overs of pulse train lines which are unavoidable in a zig-zag arrangement in respect of the transfer direction.
The multi-phase principle which here too has been used throughout with at least two electrodes per bit does, however, require a large spatial outlay. Therefore, it has been attempted to find ways of realizing a structure comprising one electrode per bit, a so-called E/B principle. This can be achieved more or less by one blank space in each shift register, into which the preceding information is in each case transferred. Here, only one information bit can be displaced for each shift register during one pulse train period. The blank position travels through the shift register in the opposite direction to the information.
This arrangement has the disadvantage, however, that each storage position must be operated by an individual pulse train. This is due to the fact that the blank position must frequently circulate through all the storage positions of this shift register, until an arbitrary information bit has arrived at the write-read station.
A realization which enables a reduction in the number of individual pulse train lines, employing the E/B principle, is known from "IEEE International Solid State Circuits Conference 1973," pages 136, 137 and 210, which describes a so-called multiplex E/B principle, in which the homologous storage positions of the shift registers lying in parallel between input and output are operated cyclically exchanged. The requisite pulse train lines are led diagonally through the storage area and, therefore, are multiply exploited. However, the disadvantage occurs that it is either necessary to provide a separate pulse generator on each side of the storage area, or that the pulse train lines must be led around the storage area, which however, cannot be effected when the length of the shift register increases as the space requirement of the pulse train lines is too great.
Another solution is to realize the multiplex E/B principle in such a manner that the parallel shift register chains arranged on the CCD module are spatially displaced by one bit position. If the pulse train lines are then led through the parallel storage positions at right angles to the shift registers, and one blank position is provided in each row of the shift register chain, the individual pulse trains can be reduced. It is easy to conceive that this is a mixed form of the pure multi-phase principle and the E/B principle.
Therefore, this arrangement has the disadvantage that there are module surfaces which are not in use and which increase in size in accordance with the length of the individual shift registers in the chain, i.e., the more consistently the E/B principle is applied and the fewer blank positions are distributed among the storage positions in each column of the storage area. Another disadvantage consists in that here only square storage area arrangements can be effected, if it is desired to produce a closed loop on the module. For these reasons, it is not considered favorable to realize the multiplex E/B principle in the described manner.
Therefore, to summarize: Conventional modules of CCD stores constructed in accordance with the multi-phase principle require at least two storage electrodes to store one information bit, and at any one time, the information is located beneath one of these electrodes. By the introduction of the E/B principle it is possible to virtually double the store density on the module for example, in comparison to the two-phase principle, as then only one electrode is required for the storage of an information bit. However, position is additionally required in the shift register to receive the preceding item of information during the shift process. The E/B principle requires a separate pulse train for each individual electrode of a shift register. The space surface requirement of the pulse train lines cancels out the gain of surface space resulting from the E/B principle.